View ISPPAC-POWR604-01T44I_3819001.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.latticesemi.com 2-1 ds1032_02.1 august 2004 data sheet ds1032 ?2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. features monitor and control multiple power supplies simultaneously monitors and sequences up to six power supplies sequence controller for power-up conditions provides four output control signals programmable digital and analog circuitry embedded pld for sequence control implements state machine and input conditional events in-system programmable (isp) through jtag and on-chip e 2 cmos embedded programmable timers two programmable 8-bit timers (32? to 524ms) programmable time delay for pulse stretching or other power supply management analog comparators for monitoring six analog comparators for monitoring 192 precise programmable threshold levels spanning 1.03v to 5.72v each comparator can be independently con?- ured around standard logic supply voltages of 1.2v, 1.5v, 1.8v, 2.5v, 3.3v, 5v other user-de?ed voltages possible six direct comparator outputs embedded oscillator built-in clock generator, 250khz programmable clock frequency programmable timer pre-scaler external clock support programmable open-drain outputs four digital outputs for logic and power supply control expandable with ispmach 4000 cpld 2.25v to 5.5v supply range in-system programmable at 3.0v to 5.5v industrial temperature range: -40? to +85? automotive temperature range: -40? to +125? 44-pin tqfp package lead-free package option application block diagram description the lattice isppac -powr604 incorporates both in- system programmable logic and in-system programma- ble analog circuits to perform special functions for power supply sequencing and monitoring. the isppac- powr604 device has the capability to be con?ured through software to control up to four outputs for power supply sequencing and six comparators monitoring sup- ply voltage limits, along with four digital inputs for inter- facing to other control circuits or digital logic. once con?ured, the design is downloaded into the device through a standard jtag interface. the circuit con?u- ration and routing are stored in non-volatile e 2 cmos. pac-designer, an easy-to-use windows-compatible software package, gives users the ability to design the logic and sequences that control the power supplies or regulator circuits. the user has control over timing func- tions, programmable logic functions and comparator threshold values as well as i/o con?urations. isppac-powr604 power sequence controller out5 out6 out7 out8 reset comp2 comp4 6 analog inputs in1 in2 in3 in4 vmon1 vmon2 vmon3 vmon4 vmon5 vmon6 clk comp3 comp1 comp6 comp5 digital logic cpu/asic card etc. por cref 0.1uf vdd vddinp 2.5-5v supply 0.1uf 1.0uf voltage monitor 6 voltage monitor 5 cpu_resetn brownout_int power_ok load_enable card_resetn done wdt_in int_ack v dd isppac-powr604 in-system programmable power supply sequencing controller and monitor
lattice semiconductor isppac-powr604 data sheet 2-2 power supply sequence controller and monitor the isppac-powr604 device is speci?ally designed as a fully-programmable power supply sequencing controller and monitor for managing up to four separate power supplies, as well as monitoring up to six analog inputs or sup- plies. the isppac-powr604 device contains an internal pld that is programmable by the user to implement digi- tal logic functions and control state machines. the internal pld connects to two programmable timers, special purpose i/o and the programmable monitoring circuit blocks. the internal pld and timers can be clocked by either an internal programmable clock oscillator or an external clock source. the voltage monitors are arranged as six independent comparators each with 192 programmable trip point set- tings. monitoring levels are set around the following standard voltages: 1.2v, 1.5v, 1.8v, 2.5v, 3.3v or 5.0v. all six voltages can be monitored simultaneously (i.e., continuous-time operation). other non-standard voltage lev- els can be accounted for using various scale factors. for added robustness, the comparators feature a variable hysteresis that scales with the voltage they monitor. generally, a larger hysteresis is better. however, as power supply voltages get smaller, that hysteresis increasingly affects trip-point accuracy. therefore, the hysteresis is +/-16mv for 5v supplies and scales down to +/-3mv for 1.2v supplies, or about 0.3% of the trip point. the programmable logic functions consist of a block of 20 inputs with 41 product terms and eight macrocells. the architecture supports the sharing of product terms to enhance the overall usability. the four output pins are open-drain outputs. these outputs can be used to drive enable lines for dc/dc converters or other control logic associated with power supply control. the four outputs are driven from the macrocells. figure 2-1. isppac-powr604 block diagram sequence controller cpld 20 i/p & 8 macrocell glb comparator outputs analog inputs clkio digital inputs 250khz internal osc 2 timers 6 6 4 5 comp1 comp2 comp3 comp4 comp5 comp6 logic out5 out6 out7 out8 isppac-powr604 vmon1 vmon2 vmon3 vmon4 vmon5 vmon6 in1 in2 in3 in4 outputs reset
lattice semiconductor isppac-powr604 data sheet 2-3 pin descriptions number name pin type voltage range description 1 nc no connect 2 nc no connect 3 nc no connect 4 nc no connect 5 vdd power 2.25v-5.5v main power supply 6 in1 cmos input vddinp 1, 3 input 1 7 in2 cmos input vddinp 1, 3 input 2 8 in3 cmos input vddinp 1, 3 input 3 9 in4 cmos input vddinp 1, 3 input 4 10 reset cmos input vdd 6 pld reset input, active low 11 vddinp power 2.25v-5.5v 3 digital inputs power supply 12 out5 8 o/d output 2.25v-5.5v 2 open-drain output 13 out6 8 o/d output 2.25v-5.5v 2 open-drain output 14 out7 8 o/d output 2.25v-5.5v 2 open-drain output 15 out8 8 o/d output 2.25v-5.5v 2 open-drain output 16 nc no connect 17 nc no connect 18 comp6 o/d output 2.25v-5.5v 2 vmon6 comparator output (open-drain) 19 comp5 o/d output 2.25v-5.5v 2 vmon5 comparator output (open-drain) 20 comp4 o/d output 2.25v-5.5v 2 vmon4 comparator output (open-drain) 21 comp3 o/d output 2.25v-5.5v 2 vmon3 comparator output (open-drain) 22 comp2 o/d output 2.25v-5.5v 2 vmon2 comparator output (open-drain) 23 comp1 o/d output 2.25v-5.5v 2 vmon1 comparator output (open-drain) 24 tck ttl/lvcmos input vdd test clock (jtag pin) 25 por o/d output 2.25v-5.5v power-on-reset output 26 clk bi-directional i/o vdd 2, 5 clock output (open-drain) or clock input 27 gnd ground ground 28 tdo ttl/lvcmos output vdd test data out (jtag pin) 29 trst ttl/lvcmos input vdd test reset, active low, 50k ohm internal pull-up (jtag pin, optional use) 30 tdi ttl/lvcmos input vdd test data in, 50k ohm pull-up (jtag pin) 31 tms ttl/lvcmos input vdd test mode select, 50k ohm internal pull-up (jtag pin) 32 vmon1 analog input 0v-5.72v 4 voltage monitor input 1 33 vmon2 analog input 0v-5.72v 4 voltage monitor input 2 34 vmon3 analog input 0v-5.72v 4 voltage monitor input 3 35 vmon4 analog input 0v-5.72v 4 voltage monitor input 4 36 vmon5 analog input 0v-5.72v 4 voltage monitor input 5 37 vmon6 analog input 0v-5.72v 4 voltage monitor input 6 38 nc no connect 39 cref reference 1.17v 7 reference for internal use, decoupling capacitor (.1uf required, cref to gnd) 40 nc no connect 41 nc no connect
lattice semiconductor isppac-powr604 data sheet 2-4 absolute maximum ratings absolute maximum ratings are shown in the table below. stresses above those listed values may cause permanent damage to the device. functional operation of the device at these or any other conditions above those indicated in the operating sections of this speci?ation is not implied. 42 nc no connect 43 nc no connect 44 nc no connect 1. in1...in4 are digital inputs to the pld. the thresholds for these pins are referenced by the voltage on vddinp. 2. the open-drain outputs can be powered independently of vdd and pulled up as high as +6.0v (referenced to ground). exception, clk pin 26 can only be pulled as high as vdd. 3. vddinp can be chosen independent of v dd. it applies only to the four logic inputs in1-in4. 4. the six vmon inputs can be biased independently of vdd. the six vmon inputs can be as high as 7.0v max (referenced to ground) . 5. clk is the pld clock output in master mode. it is re-routed as an input in slave mode. the clock mode is set in software duri ng design time. in output mode it is an open-drain type pin and requires an external pull-up resistor (pullup voltage must be v dd ). multiple isppac- powr604 devices can be tied together with one acting as the master, the master can use the internal clock and the slave can be clocked by the master. the slave needs to be set up using the clock as an input. 6. reset is an active low input pin, external pull-up resistor required. when driven low it resets all internal pld ?p-?ps to zero, a nd may turn ?n or ?ff the output pins, depending on the polarity con?uration of the outputs in the pld. if a reset function is ne eded for the other devices on the board, the pld inputs and outputs can be used to generate these signals. the reset connected to the por pin can be used if multiple isppac-powr604 devices are cascaded together in expansion mode or if a manual reset button is needed to res et the pld logic to the initial state. while using the isppac-powr604 in hot-swap applications it is recommended that either the reset pin be connected to the por pin, or connect a capacitor to ground (such that the time constant is 10 ms with the pull-up resistor) from the reset pin. 7. the cref pin requires a 0.1? capacitor to ground, near the device pin. this reference is used internally by the device. no a dditional external circuitry should be connected to this pin. 8. the four digital outputs (pins 12-15) are named out5-out8 to match isppac-powr1208 pin names and to allow easy design migrati on. symbol parameter conditions min. max. units vdd core supply voltage at pin -0.5 6.0 v vdd inp 1 digital input supply voltage for in1-in4 -0.5 6.0 v v in 2 input voltage applied, digital inputs -0.5 6.0 v vmon input voltage applied, v mon voltage monitor inputs -0.5 7.0 v v tri tristated or open drain output, external voltage applied (clk pin 26 pull-up vdd). -0.5 6.0 v t s storage temperature -65 150 ? t a ambient temperature with power applied -55 125 ? t sol maximum soldering temperature (10 sec. at 1/16 in.) 260 ? 1. v ddinp is the supply pin that controls logic inputs in1-in4 only. place 0.1? capacitor to ground and supply the v ddinp pin with appropriate supply voltage for the given input logic range. 2. digital inputs are tolerant up to 5.5v, independent of the v ddinp voltage. pin descriptions (continued) number name pin type voltage range description
lattice semiconductor isppac-powr604 data sheet 2-5 recommended operating conditions analog speci?ations over recommended operating conditions reference voltage monitors symbol parameter conditions min. max. units v dd core supply voltage at pin 2.25 5.5 v v ddprog 1 core supply voltage at pin during e 2 cell programming 3.0 5.5 v v ddinp 2 digital input supply voltage for in1-in4 2.25 5.5 v v in 3 input voltage digital inputs 0 5.5 v v mon voltage monitor inputs v mon1 - v mon6 0 6.0 v erase/program cycles eeprom, programmed at v dd = 3.0v to 5.5v -40? to +85? 1000 cycles t aprog ambient temperature during programming -40 +85 ? t a ambient temperature power applied - industrial -40 +85 ? power applied - automotive -40 +125 ? 1. the isppac-powr604 device must be powered from 3.0v to 5.5v during programming of the e 2 cmos memory. 2. v ddinp is the supply pin that controls logic inputs in1-in4 only. place 0.1? capacitor to ground and supply the v ddinp pin with appropriate supply voltge for the given input logic range. 3. digital inputs are tolerant up to 5.5v, independent of the v ddinp voltage. symbol parameter conditions min. typ. max. units i dd supply current internal clock = 250khz 5 10 ma symbol parameter conditions min. typ. max. units v ref 1 reference voltage at cref pin t = 25? 1.17 v 1. cref pin requires a 0.1? capacitor to ground. symbol parameter conditions min. typ. max. units r in input impedance 70 100 130 k v mon range programmable voltage monitor trip point (192 steps) 1.03 5.72 v v mon accuracy absolute accuracy of any trip point t = 25 ?, v dd = 3.3v -0.9 +0.9 % v mon tempco 1 temperature drift of any trip point -40? to +85? 50 ppm/ ? -40? to +125? 76 ppm/ ? hyst hysteresis of v mon input, v hyst = hyst*v mon (+/-3 to +/-13mv) v dd = 3.3v, 25? +/- 0.3% of trip point setting % psr trip point sensitivity to v dd v dd = 3.3v 0.06 %/v 1. see typical performance curves.
lattice semiconductor isppac-powr604 data sheet 2-6 power-on-reset ac/transient characteristics over recommended operating conditions digital speci?ations over recommended operating conditions symbol parameter conditions min. typ. max. units v lpor v dd supply threshold beyond which por output is guaranteed to be driven low v dd ramping up 1 1.15 v v hpor v dd supply threshold above which por output is guaranteed driven high, and device initializes v dd ramping up 1 2.1 v 1. por tests run with 10k resistor pulled up to v dd. symbol parameter conditions min. typ. max. units. voltage monitors t pd5 propagation delay. output transitions after a step input. glitch ?ter set to 5?. 1 input v trip + 100mv to v trip - 100mv ?s t pd20 propagation delay. output transitions after a step input. glitch ?ter set to 20us. 1 input v trip + 100mv to v trip - 100mv ?0s oscillators f clk internal master clock frequency note 2 230 330 khz pldclk range programmable frequency range of pld clock (8 binary steps) internal osc 250khz 1.95 250 khz pldclkext max frequency of applied external clock source external clock applied 1 mhz timers timeout range range of programmable time-out duration (15 steps) internal osc 250khz 0.03 524 ms 1. see typical performance graphs. 2. f clk frequency deviation with respect to vdd, 0.4%/volt, typical. symbol parameter conditions min. typ. max. units i il, i ih input or i/o leakage current, no pull- up 0v v in v ddinp or v dd 25 ? +/-10 ? i pu input pull-up current (tms, tdi, trst ) 25 ? 70 ? v ol open-drain output set low i sinkout = 4ma 0.4 v i sinkout maximum sink current for logic out- puts [out5-out8], [comp1- comp6] (note 1) 20 ma i sinktotal total combined sink currents from all outputs [out, comp] (note 1) 80 ma 1. [out5-out8] and [comp1-comp6] can sink up to 20ma max. per pin for leds, etc. however, output voltage levels may exceed v ol . total combined sink currents from all outputs (out, comp) should not exceed i sinktotal .
lattice semiconductor isppac-powr604 data sheet 2-7 dc input levels: in1-in4 transient characteristics over recommended operating conditions standard v il (v) v ih (v) min. max. min. max. cmos, lvcmos3.3, lvttl, ttl -0.3 0.8 2.0 5.5 lvcmos2.5 -0.3 0.7 1.7 5.5 note: v ddinp is the input supply pin for in1-in4 digital logic input pins. the logic threshold trip point of in1-in4 is dependent on the vo ltage at v ddinp. symbol parameter conditions min. typ. max. units pld timing digital glitch filter minimum pulse width to transition through glitch ?ter. applied to in1-in4 20 ? t co clock to out delay. rising edge of clock to output transition. stable input before clock edge (note 1) 300 ns t su time that input needs to be present when using a registered function with the clock. data valid before clock (note 1) 20 ? t h time that input needs to be held valid after the clock edge when using a registered function with the clock. hold data after clock 0 ? t pd propagation delay internal to the embedded pld 90 ns t rst reset pulse width 25 ? 1. external clock 1mhz. open drain outputs with 2k pull-up resistor to v dd . note: all the above parameters apply to signal paths from the digital inputs [in1-in4].
lattice semiconductor isppac-powr604 data sheet 2-8 timing for jtag operations symbol parameter conditions min typ. max units t ckmin minimum clock period 1 s t ckh tck high time 200 ns t ckl tck low time 200 ns t mss tms setup time 15 ns t msh tms hold time 50 ns t dis tdi setup time 15 ns t dih tdi hold time 50 ns t dozx tdo ?at to valid delay 200 ns t dov tdo valid delay 200 ns t doxz tdo valid to ?at delay 200 ns t rstmin minimum reset pulse width 40 ns t pwp time for a programming operation 1 40 100 ms t pwe time for an erase operation 40 100 ms 1. t pwp represents programming pulse width for a single row of e 2 cmos cells. t ck t mss t mss t mss t msh t dis t dih t ckh t ckmin t ckl t ms t ck t ms t di t do t dozh t doxz t dov t pwp, t pwe program and erase cycles executed in run-test/idle
lattice semiconductor isppac-powr604 data sheet 2-9 typical performance graphs 0 25 10 -1 -0.8 -0.6 -0.4 -0.2 0 1 0.2 0.4 0.6 0.8 20 50 100 200 50 75 100 125 propagation delay ( s) count input overdrive (mv) trip point error % propagation delay vs. overdrive v mon trip point error 25 c glitch filter = 20 s glitch filter = 5 s note: typical propagation delay of v mon inputs to outputs as a function of overdrive beyond selected trip point. % error temperature ( c) typical v mon comparator trip point accuracy vs. temperature -50 0 50 100 150 0 1000 2000 3000 4000 5000 6000 7000 -0.5 0 0.5 1 1.5 2 2.5 3
lattice semiconductor isppac-powr604 data sheet 2-10 table 2-1. v mon trip point table 1 table 2-1 shows all possible comparator trip point voltage settings. the internal resistive divider allows ranges for 1.2v, 1.8v, 2.5v, 3.3v and 5.0v. there are 192 available voltages, ranging from 1.036v to 5.723v. in addition to the 192 voltage monitor trip points, the user can add additional resistors outside the device to divide down the voltage and achieve virtually any voltage trip point. this allows the capability to monitor higher voltages such and 12v, 15v, 24v, etc. voltage monitor trip points are set in the graphical user interface of the pac-designer software by simple pull-down menus. the user simply selects the given range and corresponding trip point value. attenuation and ref- erence values are set internally using e 2 cmos con?uration bits internal to the device. figure 2-2 shows a single comparator, the attenuation network and reference used to program the monitor trip points. each of the six comparators are independently set in the same way. theory of operation the isppac-powr604 incorporates programmable voltage monitors along with digital inputs and outputs. the eight macrocell pld inputs are from the six voltage monitors and four digital inputs. there are two embedded pro- grammable timers that interface with the pld, along with an internal programmable oscillator. the six independently programmable voltage monitors each have 192 programmable trip points. figure 2-2 shows a simpli?d schematic representation of one of these monitors. 1.2 low 1.2 high 1.5 low 1.5 high 1.8 low 1.8 high 2.5 low 2.5 high 3.3 low 3.3 high 5.0 low 5.0 high 1.036 1.202 1.291 1.502 1.549 1.801 2.153 2.500 2.842 3.297 4.299 4.991 1.046 1.213 1.303 1.516 1.564 1.818 2.173 2.524 2.869 3.328 4.340 5.038 1.056 1.225 1.316 1.531 1.579 1.836 2.195 2.549 2.897 3.361 4.383 5.088 1.066 1.237 1.329 1.546 1.595 1.854 2.216 2.574 2.926 3.394 4.426 5.138 1.076 1.249 1.341 1.560 1.609 1.871 2.237 2.597 2.952 3.425 4.466 5.185 1.087 1.261 1.354 1.575 1.625 1.889 2.258 2.622 2.981 3.458 4.509 5.235 1.096 1.272 1.366 1.590 1.639 1.906 2.279 2.646 3.008 3.489 4.550 5.282 1.107 1.284 1.379 1.605 1.655 1.924 2.300 2.671 3.036 3.522 4.593 5.332 1.117 1.295 1.391 1.619 1.669 1.941 2.320 2.694 3.063 3.553 4.633 5.379 1.127 1.307 1.404 1.634 1.685 1.959 2.342 2.719 3.091 3.586 4.676 5.429 1.137 1.319 1.417 1.649 1.700 1.977 2.363 2.744 3.120 3.619 4.719 5.479 1.147 1.331 1.429 1.663 1.715 1.994 2.384 2.768 3.147 3.650 4.760 5.526 1.157 1.343 1.442 1.678 1.730 2.012 2.405 2.793 3.175 3.683 4.803 5.576 1.168 1.355 1.455 1.693 1.746 2.030 2.427 2.818 3.203 3.716 4.846 5.626 1.178 1.366 1.467 1.707 1.761 2.047 2.447 2.841 3.230 3.747 4.886 5.673 1.188 1.378 1.480 1.722 1.776 2.065 2.469 2.866 3.259 3.780 4.929 5.723 1.all possible comparator trip voltages using internal attenuation settings.
lattice semiconductor isppac-powr604 data sheet 2-11 figure 2-2. voltage monitors each monitor consists of three major subsystems. the core of the monitor is a voltage comparator. this compara- tor outputs a high signal to the pld array if the voltage at its positive terminal is greater than that at its negative terminal, otherwise it outputs a low signal. a small amount of hysteresis is provided by the comparator to reduce the effects of input noise. the input signal is attenuated by a programmable resistive divider before it is fed into the comparator. this feature is used to determine the coarse range in which the comparator should trip (e.g. 1.8v, 3.3v, 5v). twelve possible ranges are available from the input divider network. the comparators negative terminal is obtained from a pro- grammable reference source (reference), which may be set to one of 16 possible values scaled in approximately 1% increments from each other, allowing for ?e tuning of the voltage monitors trip points. this combination of coarse and ?e adjustment supports 192 possible trip-point voltages for a given monitor circuit. because each monitors reference and input divider settings are completely independent of those of the other monitor circuits, the user can set any input monitor to any of the 192 available settings. comparator hysteresis pld architecture the isppac-powr604 digital logic is composed of an internal pld that is programmed to perform the sequencing functions. the pld architecture allows ?xibility in designing various state machines and control logic used for monitoring. the macrocell shown in figure 2-3 is the heart of the pld. there are eight macrocells that can be used v mon range setting 1 typical hysteresis on over voltage range typical hysteresis on under voltage range units 5.0v +/- 16.2 +/- 14.0 mv 3.3v +/- 10.7 +/- 9.2 mv 2.5v +/- 8.1 +/- 7.0 mv 1.8v +/- 5.8 +/- 5.0 mv 1.5v +/- 4.9 +/- 4.2 mv 1.2v +/- 3.9 +/- 3.4 mv 1. the hysteresis scales depending on the voltage monitor range that is selected. the values show are typical and are centered around the nominal voltage trip point for a given range selection. to pld array reference monitor voltage vmon1..vmon6 3mv hysteresis
lattice semiconductor isppac-powr604 data sheet 2-12 to control the functional states of the sequencer state machine or other control or monitoring logic. the pld and array shown in figure 2-4 has 20 inputs and 41 product terms (pts). the resources from the and array feed the eight macrocells. the resources within the macrocells share routing and contain a product-term allocation array. the product term allocation array greatly expands the plds ability to implement complex logical functions by allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions. the basic macrocell has ?e product terms that feed the or gate and the ?p-?p. the ?p-?p in each macrocell is independently con?ured. it can be programmed to function as a d-type or t-type ?p-?p. the combinatorial func- tions are achieved through the bypass mux function shown. by having the polarity control xor, the logic reduction can be best ? to minimize the number of product terms. the ?p-?ps clock drives from a common clock that can be generated from a pre-scaled, on-board clock source or from an external clock. the macrocell also supports asynchronous reset and preset functions, derived from product terms, the global reset input, or the power-on reset signal. figure 2-3. isppac-powr604 macrocell block diagram pt0 pt1 pt2 pt3 pt4 d/t q r p to orp clk clock polarity macrocell flip-flop provides d,t or combinatorial output with polarity product-term allocation global reset power on reset global polarity fuse for init product-term block init product-term
lattice semiconductor isppac-powr604 data sheet 2-13 figure 2-4. pld and timer functional block diagram mc0 mc1 mc2 mc3 mc4 mc5 mc6 mc7 2 8 in[1:4] vmon[1:6] comparators 4 6 output routing pool por/reset and array 20 inputs 41 pt 8 outputs timer1 clock generation routing pool blk-init pt timer2 8 out5 out6 out7 out8
lattice semiconductor isppac-powr604 data sheet 2-14 clock and timer systems figure 2-5 shows a block diagram of the isppac-powr604s internal clock and timer systems. the pld clock can be programmed with eight different frequencies based on the internal oscillator frequency of 250khz. figure 2-5. clock and timer block table 2-2. pld clock prescaler 1 the internal oscillator runs at a ?ed frequency of 250khz. this main signal is then fed to the pld clock pre-scaler and also the timer clock pre-scaler (figure 2-5). for the pld clock, the main 250khz oscillator is divided down to eight selectable frequencies shown in the table 2-2. the architecture of the clock network allows the pld clock to be driven to the clk pin. this enables the user access to the pld clock as an output for expansion mode or other uses of the (clk) clock pin. schematically, when the switch is in the upper position, the internal oscillator drives the pld clock pre-scaler and the timer pre-scaler. in this mode, the clk pin is an open-drain output and represents the same frequency as the pld clock. this is used when operating other devices (such as ?lave sequencing devices) in a synchronized mode. when the switch is in the lower position, the clk pin is an input and must be driven with an external clock source. when driven from an external source, the same pld clock pre-scaler is available to this external clock. the frequencies available for the pld clock will be the external clock frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128, depending on the programmable value chosen. the timer clock pre-scaler divides the internal 250khz oscillator (or external clock, if selected) down before it gen- erates the clock for the two programmable timers. the pre-scaler has eight different divider ratios: divide by 4, 8, 16, 32, 64, 128, 256 and 512 (table 2-3). after the clock for the timers is divided down, it is used to drive the pro- grammable timers. the two timers share the same timer clock frequency but may have different end count values. pld clock frequency (khz) pld prescaler divider 250 1 125 2 62.5 4 31.3 8 15.6 16 7.8 32 3.9 64 2 128 1. values based on 250khz clock. internal osc 250khz timer prescaler (time out range) pld clock prescaler clk timer1 timer2
lattice semiconductor isppac-powr604 data sheet 2-15 the timers can cover a range from 32us to 524ms for the internal oscillator. longer delays can be achieved by using the external clock as an input. table 2-3. timer values 1 for design entry, the user can select the source for the clock and the pac-designer software will calculate the appropriate delays in an easy-to-select menu format. the control inputs for timer1 and timer2 can be driven by any of the eight pld macrocell outputs. the reset for the timers is a function of the global reset pin (reset ), a power-on reset or when the timer input goes low. the wave- forms in figure 2-6 show the basic timer start and reset functions. timer and clock divider values are speci?d in during the design phase using the pac-designer software, while simple pull-down menus allow the user to select the clocking mode and the values for the timers and the pld clock. figure 2-6. timer waveforms note that if the clock module is con?ured as ?lave (i.e. the clk is an input), the actual time-out of the two timers is determined by the external clock frequency. 4 62 khz 8 31.2 khz 16 15.6 khz 32 7.8 khz 64 3.9 khz 128 2 khz 256 1 khz 512 0.5 khz 0.032 ms 0.064 ms 0.064 ms 0.128 ms 0.128 ms 0.128 ms 0.256 ms 0.256 ms 0.256 ms 0.256 ms 0.512 ms 0.512 ms 0.512 ms 0.512 ms 0.512 ms 1.024 ms 1.024 ms 1.024 ms 1.024 ms 1.024 ms 1.024 ms 2.048 ms 2.048ms 2.048ms 2.048ms 2.048ms 2.048ms 2.048ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms 8.192 ms 8.192 ms 8.192 ms 8.192 ms 8.192 ms 8.192 ms 8.192 ms 16.384 ms 16.384 ms 16.384 ms 16.384 ms 16.384 ms 16.384 ms 32.768 ms 32.768 ms 32.768 ms 32.768 ms 32.768 ms 65.536 ms 65.536 ms 65.536 ms 65.536 ms 131.072 ms 131.072 ms 131.072 ms 262.144 ms 262.144 ms 524.288 ms 1. timer values based on 250khz clock. timer period timer gate timer output timer period (from pld) (to pld) start timer timer expired reset timer programmabletimer delay start timer timer expired programmabletimer delay
lattice semiconductor isppac-powr604 data sheet 2-16 ieee standard 1149.1 interface in-system programming of the isppac-powr604 is facilitated via an ieee 1149.1 test access port (tap). it is used by the isppac-powr604 as a serial programming interface, boundary scan test is not supported. there are no boundary scan logic registers in the isppac-powr604 architecture. this does not prevent the isppac-powr604 from functioning correctly, however, when placed in a valid serial chain with other ieee 1149.1 compliant devices. since the isppac-powr604 is used to powerup other devices, it should be programmed in a separate chain from plds, fpgas or other jtag devices. a brief description of the isppac-powr604 serial interface follows. for complete details of the reference speci?a- tion, refer to the publication, standard test access port and boundary-scan architecture, ieee std 1149.1-1990 (which now includes ieee std 1149.1a-1993). overview an ieee 1149.1 test access port (tap) provides the control interface for serially accessing the digital i/o of the isp- pac-powr604. the tap controller is a state machine driven with mode and clock inputs. instructions are shifted into an instruction register, which then determines subsequent data input, data output, and related operations. device programming is performed by addressing various registers, shifting data in, and then executing the respec- tive program instruction. the programming instructions transfer the data into internal e 2 cmos memory. it is these non-volatile memory cells that determine the con?uration of the isppac-powr604. by cycling the tap controller through the necessary states, data can also be shifted out of the various registers to verify the current isppac- powr604 con?uration. instructions exist to access all data registers and perform internal control operations. for compatibility between compliant devices, two data registers are mandated by the ieee 1149.1 speci?ation. other registers are functionally speci?d, but inclusion is strictly optional. finally, there are provisions for optional user data registers that are de?ed by the manufacturer. the two required registers are the bypass and boundary- scan registers. for isppac-powr604, the bypass register is a 1-bit shift register that provides a short path through the device when boundary testing or other operations are not being performed. the isppac-powr604, as men- tioned earlier has no boundary-scan logic and therefore no boundary scan register. all instructions relating to boundary scan operations place the isppac-powr604 in the bypass mode to maintain compliance with the speci?ation. the optional identi?ation (idcode) register described in ieee 1149.1 is also included in the isppac-powr604. six additional user data registers are included in the tap of the isppac-powr604 as shown in figure 2-7. most of these additional registers are used to program and verify the analog con?uration (cfg) and pld bits. a status register is also provided to read the status of the six analog comparators.
lattice semiconductor isppac-powr604 data sheet 2-17 figure 2-7. tap registers tap controller speci?s the tap is controlled by the test clock (tck) and test mode select (tms) inputs. these inputs determine whether an instruction register or data register operation is performed. driven by the tck input, the tap consists of a small 16-state controller. in a given state, the controller responds according to the level on the tms input as shown in figure 2-8. test data in (tdi) and tms are latched on the rising edge of tck, with test data out (tdo) becom- ing valid on the falling edge of tck. there are six steady states within the controller: test-logic-reset, run-test/ idle, shift-data-register, pause-data-register, shift-instruction-register, and pause-instruction-register. but there is only one steady state for the condition when tms is set high: the test-logic-reset state. this allows a reset of the test logic within ?e tcks or less by keeping the tms input high. test-logic-reset is the power-on default state. when the correct logic sequence is applied to the tms and tck inputs, the tap will exit the test-logic-reset state and move to the desired state. the next state after test-logic-reset is run-test/idle. until a data or instruction scan is performed, no action will occur in run-test/idle (steady state = idle). after run-test/idle, either a data or instruction scan is performed. the states of the data and instruction register blocks are identical to each other dif- fering only in their entry points. when either block is entered, the ?st action is a capture operation. for the data registers, the capture-dr state is very simple; it captures (parallel loads) data onto the selected serial data path (previously chosen with the appropriate instruction). for the instruction register, the capture-ir state will always load the idcode instruction. it will always enable the id register for readout if no other instruction is loaded prior status register (6 bits) idcode register (32 bits) ues register (16 bits) cfg register (17 bits) cfg address register (4 bits) pld data register (41 bits) pld address register (43 bits) bypass register (1 bit) test access port (tap) logic output latch multiplexer analog configuration e 2 non-volatile memory (68 bits) pld and / arch e 2 non-volatile memory (1763 bits) instruction register (6 bits) analog comparator array (6 bits) tdi tck tms tdo
lattice semiconductor isppac-powr604 data sheet 2-18 to a shift-dr operation. this, in conjunction with mandated bit codes, allows a ?lind interrogation of any device in a compliant ieee 1149.1 serial chain. figure 2-8. tap states from the capture state, the tap transitions to either the shift or exit1 state. normally the shift state follows the capture state so that test data or status information can be shifted out or new data shifted in. following the shift state, the tap either returns to the run-test/idle state via the exit1 and update states or enters the pause state via exit1. the pause state is used to temporarily suspend the shifting of data through either the data or instruction register while an external operation is performed. from the pause state, shifting can resume by re-entering the shift state via the exit2 state or be terminated by entering the run-test/idle state via the exit2 and update states. if the proper instruction is shifted in during a shift-ir operation, the next entry into run-test/idle initiates the test mode (steady state = test). this is when the device is actually programmed, erased or veri?d. all other instructions are executed in the update state. test instructions like data registers, the ieee 1149.1 standard also mandates the inclusion of certain instructions. it outlines the function of three required and six optional instructions. any additional instructions are left exclusively for the manu- facturer to determine. the instruction word length is not mandated other than to be a minimum of two bits, with only the bypass and extest instruction code patterns being speci?ally called out (all ones and all zeroes respec- tively). the isppac-powr604 contains the required minimum instruction set as well as one from the optional instruction set. in addition, there are several proprietary instructions that allow the device to be con?ured, veri?d, and monitored. for isppac-powr604, the instruction word length is 6-bits. all isppac-powr604 instructions available to users are shown in table 2-4. 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 0 1 update-ir exit2-ir pause-ir exit1-ir shift-ir capture-ir select-ir-scan update-dr exit2-dr pause-dr exit1-dr shift-dr capture-dr select-dr-scan run-test/idle test-logic-reset note: the value shown adjacent to each state transition represents the signal present at tms at the time of a rising edge at tck.
lattice semiconductor isppac-powr604 data sheet 2-19 table 2-4. isppac-powr604 tap instruction table bypass is one of the three required instructions. it selects the bypass register to be connected between tdi and tdo and allows serial data to be transferred through the device without affecting the operation of the isppac- powr604. the ieee 1149.1 standard de?es the bit code of this instruction to be all ones (111111). the required sample/preload instruction dictates the boundary-scan register be connected between tdi and tdo. the isppac-powr604 has no boundary scan register, so for compatibility it defaults to the bypass mode whenever this instruction is received. the bit code for this instruction is de?ed by lattice as shown in table 2-4. the extest (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary scan register to be connected between tdi and tdo. again, since the isppac-powr604 has no boundary scan logic, the device is put in the bypass mode to ensure speci?ation com- patibility. the bit code of this instruction is de?ed by the 1149.1 standard to be all zeros (000000). the optional idcode (identi?ation code) instruction is incorporated in the isppac-powr604 and leaves it in its functional mode when executed. it selects the device identi?ation register to be connected between tdi and tdo. the identi?ation register is a 32-bit shift register containing information regarding the ic manufacturer, instruction code description extest 000000 external test. defaults to bypass. addpld 1 000001 address pld address register (43 bits). datapld 1 000010 address pld column data register (81 bits). eraseand 1, 2 000011 bulk erase and array. erasearch 1, 2 000100 bulk erase architect array. progpld 1, 2 000101 program pld column data register into e 2 . progesf 1, 2 000110 program the electronic security fuse bit. bypass 000111 bypass (connect tdi to tdo). readpld 1 001000 reads pld column data from e 2 to the register (81 bits). discharge 1 001001 fast vpp discharge. addcfg 1 001010 address cfg array address (4 bits). datac f g 1 001011 address cfg data (41 bits). erasecfg 1, 2 001100 bulk erase cfg data. progcfg 1, 2 001101 program cfg data register into e 2 . readcfg 1 001110 read cfg column data from e 2 to the register (41 bits). cfgbe 1, 2 010110 bulk erase all e 2 memory (cfg, pld, use, and esf). safestate 1 010111 digital outputs hiz (fet pulled l) programen 1 011000 enable program mode (safestate io) idcode 011001 address identi?ation code data register (32 bits). programdis 011010 disable program mode (normal io) addstatus 011011 address status register (6 bits). sample 011100 sample/preload. default to bypass. eraseues 1, 2 011101 bulk erase ues. shiftues 011110 reads ues data from e 2 and selects the ues register (16 bits). progues 1, 2 011111 program ues data register into e 2 . bypass 1xxxxx bypass (connect tdi to tdo). 1. when these instructions are executed, the outputs are placed in the same mode as the instruction safestate (as described later) to prevent invalid and potentially destructive power supply sequencing. 2. instructions that erase or program the e 2 cmos memory must be executed only when the supply to the device is maintained at 3.0v to 5.5v.
lattice semiconductor isppac-powr604 data sheet 2-20 device type and version code (figure 2-9). access to the identi?ation register is immediately available, via a tap data scan operation, after power-up of the device, or by issuing a test-logic-reset instruction. the bit code for this instruction is de?ed by lattice as shown in table 2-4. figure 2-9. id code isppac-powr604 speci? instructions there are 21 unique instructions speci?d by lattice for the isppac-pwr604. these instructions are primarily used to interface to the various user registers and the e 2 cmos non-volatile memory. additional instructions are used to control or monitor other features of the device. a brief description of each unique instruction is provided in detail below, and the bit codes are found in table 2-4. addpld ?this instruction is used to set the address of the pld and/arch arrays for subsequent program or read operations. this instruction also forces the outputs into the safestate. datapld ?this instruction is used to shift pld data into the register prior to programming or reading. this instruction also forces the outputs into the safestate. eraseand ?this instruction will bulk erase the pld and array. the action occurs at the second rising edge of tck in run-test-idle jtag state. the device must already be in programming mode programen instruction). this instruction also forces the outputs into the safestate. erasearch ?this instruction will bulk erase the pld arch array. the action occurs at the second rising edge of tck in run-test-idle jtag state. the device must already be in programming mode (programen instruction). this instruction also forces the outputs into the safestate. progpld ?this instruction programs the selected pld and/arch array column. the speci? column is prese- lected by using addpld instruction. the programming occurs at the second rising edge of the tck in run-test- idle jtag state. the device must already be in programming mode (programen instruction) and operated at 3.3v to 5.0v. this instruction also forces the outputs into the safestate. progesf ?this instruction is used to program the electronic security fuse (esf) bit. programming the esf bit protects proprietary designs from being read out. the programming occurs at the second rising edge of the tck in run-test-idle jtag state. the device must already be in programming mode (programen instruction). this instruction also forces the outputs into the safestate. readpld ?this instruction is used to read the content of the selected pld and/arch array column. this spe- ci? column is preselected by using addpld instruction. this instruction also forces the outputs into the saf- estate. discharge ?this instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares isppac-powr604 for a read cycle. this instruction also forces the outputs into the safestate. xxxx / 0000 0001 0100 0001 / 0000 0100 001 / 1 msb lsb version (4 bits) e 2 configured part number (16 bits) 0141h = isppac-powr604 jedec manufacturer identity code for lattice semiconductor (11 bits) constant 1 (1 bit) per 1149.1-1990
lattice semiconductor isppac-powr604 data sheet 2-21 addcfg ?this instruction is used to set the address of the cfg array for subsequent program or read operations. this instruction also forces the outputs into the safestate. datacfg ?this instruction is used to shift data into the cfg register prior to programming or reading. this instruction also forces the outputs into the safestate. erasecfg ?this instruction will bulk erase the cfg array. the action occurs at the second rising edge of tck in run-test-idle jtag state. the device must already be in programming mode (programen instruction). this instruction also forces the outputs into the safestate. progcfg ?this instruction programs the selected cfg array column. this speci? column is preselected by using addcfg instruction. the programming occurs at the second rising edge of the tck in run-test-idle jtag state. the device must already be in programming mode (programen instruction). this instruction also forces the outputs into the safestate. readcfg ?this instruction is used to read the content of the selected cfg array column. this speci? column is preselected by using addcfg instruction. this instruction also forces the outputs into the safestate. cfgbe ?this instruction will bulk erase all e 2 cmos bits (cfg, pld, ues, and esf) in the isppac-powr604. the device must already be in programming mode (programen instruction). this instruction also forces the out- puts into the safestate. safestate ?this instruction turns off all of the open-drain output transistors. pins that are programmed as fet drivers will be placed in the active low state. this instruction is effective after update-instruction-register jtag state. programen ?this instruction enables the programming mode of the isppac-powr604. this instruction also forces the outputs into the safestate. idcode ?this instruction connects the output of the identi?ation code data shift (idcode) register to tdo (figure 2-10), to support reading out the identi?ation code. figure 2-10. idcode register programdis ?this instruction disables the programming mode of the isppac-powr604. the test-logic-reset jtag state can also be used to cancel the programming mode of the isppac-powr604. addstatus ?this instruction is used to both connect the status register to tdo (figure 2-11) and latch the 6 voltage monitor (comparator outputs) into the status register. latching of the 6 comparator outputs into the status register occurs during capture-data-register jtag state. figure 2-11. status register eraseues ?this instruction will bulk erase the content of the ues e 2 cmos memory. the device must already be in programming mode (programen instruction) and operated. this instruction also forces the outputs into the safestate. shiftues ?this instruction both reads the e 2 cmos bits into the ues register and places the ues register between the tdi and tdo pins (as shown in figure u), to support programming or reading of the user electronic signature bits. tdo bit 0 bit 1 bit 2 bit 3 bit 4 bit 27 bit 28 bit 29 bit 30 bit 31 tdo vmon 6 vmon 5 vmon 4 vmon 3 vmon 2 vmon 1
lattice semiconductor isppac-powr604 data sheet 2-22 figure 2-12. ues register progues ?this instruction will program the content of the ues register into the ues e 2 cmos memory. the device must already be in programming mode (programen instruction). this instruction also forces the outputs into the safestate. notes: in all of the descriptions above, safestate refers both to the instruction and the state of the digital output pins, in which the open-drains are tri-stated and the fet drivers are pulled low. before any of the above programming instructions are executed, the respective e 2 cmos bits need to be erased using the corresponding erase instruction. application example the isppac-powr604 device has six comparators to monitor various power supply levels. the comparators each have a programmable trip point that is programmed by the user at design time. the output of the comparators feed into the pld logic array to drive the state machine logic or monitor logic. the outputs of comparators comp1...comp6 are also routed to external pins to be monitored directly or can be used to drive additional control logic if expansion is required. the comparator outputs are open-drain type output buffers and require a pull up resistor to drive a logic high. all six comparators have hysteresis, the hysteresis is dependent on the voltage trip point scale that is set, it ranges from 3.4mv for the 1.2v monitor supply range to 16.2mv for the 5.0v monitor sup- ply range. the comparators can be set with a trip point from 1.03v to 5.72v, with 192 different values. the applica- tion diagram shows a set-up that can monitor and control multiple power supplies. the digital outputs and inputs are also used to interface with the board that is being powered up. tdo bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15
lattice semiconductor isppac-powr604 data sheet 2-23 figure 2-13. typical application example: isppac-powr604 interfacing to cpu board using four outputs, four inputs and six vmon voltage monitoring signals isppac-powr604 power sequence controller out5 out6 out7 out8 reset comp2 comp4 6 analog inputs in1 in2 in3 in4 vmon1 vmon2 vmon3 vmon4 vmon5 vmon6 clk comp3 comp1 comp6 comp5 digital logic cpu/asic card etc. por cref 0.1uf vdd vddinp 2.5-5v supply 0.1uf 1.0uf voltage monitor 6 voltage monitor 5 cpu_resetn brownout_int power_ok load_enable card_resetn done wdt_in int_ack v dd
lattice semiconductor isppac-powr604 data sheet 2-24 software-based design environment design entry software all functions within the isppac-powr604 are controlled through a windows-based software development tool called pac-designer. pac-designer has an easy-to-use graphical user interface (figure 2-14) that allows the user to set up the isppac-powr604 to perform required functions, such as timed sequences for power supply or moni- tor trip points for the voltage monitor inputs. the software tool gives the user control over how the device drives the outputs and the functional con?urations for all i/o pins. user-friendly dialog boxes are provided to set and edit all of the analog features of the isppac-powr604. an extension to the schematic screen is the logibuilder design environment (figure 2-15) that is used to enter and edit control sequences. again, user-friendly dialog boxes are provided in this window to help the designer quickly implement sequences that take advantage of the powerful built-in pld. once the con?urations are chosen and the sequence has been described by the utilities, the device is ready to program. a standard jtag interface is used to program the e 2 cmos memory. the pac-designer soft- ware supports downloading the device through the pcs parallel port. the isppac-powr604 can be repro- grammed in-system using the software and an ispdownload cable assembly to compensate for variations in supply timing, sequencing or scaling of voltage monitor inputs. figure 2-14. pac-designer schematic screen the user interface (figure 2-14) provides access to various internal function blocks within the isppac-powr604 device. analog inputs : accesses the programmable threshold trip-points for the comparators and pin naming conven- tions. digital inputs : digital input naming con?urations and digital inputs feed into the internal pld for the sequence controller. sequence controller : incorporates a pld architecture for designing the state machine to control the order and functions associated with the user-de?ed power-up sequence/monitor and control. logic outputs : these pins are con?ured and assigned in the logic output functional block. the four digital out- puts are open-drain and require an external pull-up resistor.
lattice semiconductor isppac-powr604 data sheet 2-25 internal clock : the internal clock con?uration and clock prescaler values are user-programmable, as well as the four internal programmable timers used for sequence delay. user electronic signature (ues) : stores 16 bits of id or board information in non-volatile e 2 cmos. figure 2-15. pac-designer logibuilder screen programming of the isppac-powr604 is accomplished using the lattice ispdownload cable. this cable con- nects to the parallel port of a pc and is driven through the pac-designer software. the software controls the jtag tap interface and shifts in the jedec data bits that set the con?uration of all the analog and digital circuitry that the user has de?ed during the design process. power to the device must be set at 3.0v to 5.5v during programming, once the programming steps have been com- pleted, the power supply to the isppac-powr604 can be set from 2.25v to 5v. once programmed, the on-chip non-volatile e 2 cmos bits hold the entire design con?uration for the digital circuits, analog circuits and trip points for comparators etc. upon powering the device up, the non-volatile e 2 cmos bits control the device con?uration. if design changes need to be made such as adjusting comparator trip points or changes to the digital logic functions, the device is simply re-programmed using the ispdownload cable. design simulation capability support for functional simulation of the control sequence is provided using the design tools waveform editor and waveform viewer. both applications are spawned from the logibuilder environment of pac-designer. the simula- tion engine combines the design ?e with a stimulus ?e (edited by the user with the waveform editor) to produce an output ?e that can be observed with the waveform viewer (figure 2-16).
lattice semiconductor isppac-powr604 data sheet 2-26 figure 2-16. pac-designer functional simulation screen in-system programming the isppac-powr604 is an in-system programmable device. this is accomplished by integrating all e 2 cmos con?uration memory and control logic on-chip. programming is performed through a 4-wire, ieee 1149.1 compli- ant serial jtag interface. once a device is programmed, all con?uration information is stored on-chip, in non-vol- atile e 2 cmos memory cells. the speci?s of the ieee 1149.1 serial interface and all isppac-powr604 instructions are described in the jtag interface section of this data sheet. user electronic signature the user electronic signature (ues), allows the designer to include identi?ation bits or serial numbers inside the device, stored in e 2 cmos memory. the isppac-powr604 contains 16 ues bits that can be con?ured by the user to store unique data such as id codes, revision numbers or inventory control codes. electronic security an electronic security fuse (esf) bit is provided to prevent unauthorized readout of the e 2 cmos bit pattern. once programmed, this cell prevents further access to the functional user bits in the device. this cell can only be erased by reprogramming the device; this way the original con?uration cannot be examined or copied once programmed. usage of this feature is optional. production programming support once a ?al con?uration is determined, an ascii format jedec ?e can be created using the pac-designer soft- ware. devices can then be ordered through the usual supply channels with the users speci? con?uration already preloaded into the devices. by virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and ?xibility in production planning.
lattice semiconductor isppac-powr604 data sheet 2-27 package diagrams 44-pin tqfp (dimensions in millimeters) 0.10 c base metal 5. the top of package may be smaller than the bottom 4. dimensions d1 and e1 do not include mold protrusion. datums a, b and d to be determined at datum plane h. allowable mold protrusion is 0.254 mm on d1 and e1 2. all dimensions are in millimeters. 1. dimensioning and tolerancing per ansi y14.5 - 1982. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from the lead tip. 7. a1 is defined as the distance from the seating plane to the lowest point on the package body. exact shape of each corner is optional. 8. dimensions. of the package by 0.15 mm. 6. section b-b: 3. section b-b b 1 c 1 c 0.45 0.40 0.16 0.20 c1 0.09 0.13 c b1 0.09 0.30 b e 0.30 0.35 0.15 0.37 0.80 bsc max. 1.60 0.15 1.45 0.75 e 12.00 bsc 0.45 l n e1 0.60 44 10.00 bsc d d1 a2 1.35 12.00 bsc 10.00 bsc 1.40 detail 'a' a1 a1 a 0.05 - symbol min. - - nom. 1.00 ref. 0.20 min. b l 0-7 seating plane lead finish 0.20 b b a-b c md side view e top view 8 d 3 a 3 d gauge plane d h a-b 4x 0.20 bottom view a2 c a see detail 'a' h b 3 e b e1 d1 0.25 a-b 0.20 c44x d notes: pin 1 indicator
lattice semiconductor isppac-powr604 data sheet 2-28 part number description isppac-powr604 ordering information conventional packaging industrial automotive lead-free packaging lead-free industrial lead-free automotive part number package pins ISPPAC-POWR604-01T44I tqfp 44 part number package pins isppac-powr604-01t44e tqfp 44 part number package pins isppac-powr604-01tn44i tqfp 44 part number package pins isppac-powr604-01tn44e tqfp 44 device number isppac-powr604 - 01xx44x operating temperature range i = industrial (-40 c to +85 c) e = automotive (-40 c to +125 c) package t = 44-pin tqfp tn = lead-free 44-pin tqfp performance grade 01 = standard device family
lattice semiconductor isppac-powr604 data sheet 2-29 package options revision history date version change summary previous lattice releases. september 2003 01.0 added 125? automotive range -40? to +125? to features bullets. added vmon tempco for 125? 76ppm to voltage monitors table. isinkout max added for logic outputs out5-8 and comparators comp 1-6, 20ma max (digital speci?ations table). spec added for isinktotal total combined sink current from all out, comp 80ma (digital speci?ations table). automotive range added to part number description section. tn suf? added for lead free packaging, part number description sec- tion. automotive part number added in the ordering information section. january 2004 02.0 ordering part number added for lead free packaging, ordering infor- mation section. august 2004 02.1 add r/c network to reset pin in application block diagram to acco- modate hot-swapping. edited note 6 in pin descriptions table to support hot-swapping. out5 out6 out7 out8 vmon1 vmon2 vmo n 3 vmo n 4 vmo n 5 vmo n 6 nc nc nc comp1 co mp2 co mp4 co mp5 co mp6 nc nc isppac-powr604 44-pin tqfp 1 44 43 42 41 40 39 38 37 35 34 33 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 36 co mp3 por nc nc nc tdi tdo tck tms trst clk cref gnd nc nc nc vdd in1 in2 in3 in4 vddinp note: nc is no connect. nc reset

▲Up To Search▲

Price & Availability of ISPPAC-POWR604-01T44I

	To Download ISPPAC-POWR604-01T44I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .